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TiWi-SL MODULE
DATASHEET
SPI HOST CONTROLLER INTERFACE
The main interface to the TiWi-SL Module is a Serial Peripheral Interface (SPI).
This section describes the SPI Host Controller interface (HCI).
Overview
The SPI interface provides high-speed data transfer capability with low power consumption for mobile
electronic devices. The SPI bus was designed to operate on a point-to-multipoint basis by providing a
separate, active-low chip select (CS) per device.
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Supported clock rate = 0-16MHz
The device interface is always an SPI Slave, host is always an SPI Master
SPI Interface Description
The SPI is based on the five-line, master/slave communication model see Figure 3
SPI_CLK
SPI_CS
Host
SPI_IRQ
Device
SPI_DO (Data Out)
SPI_DI (Data In)
Figure 3 SPI Interface Signals
SPI Line Description
Port Name
SPI_CLK
SPI_DI
SPI_CS(1)
SPI_IRQ(2)
SPI_DO
Input/Output
Input
Input
Input
Output
Output
Description
Clock (0 MHz to 16MHz) from host to device
Data from host to device (MOSI)
CS signal from host to device (active low)
Interrupt from device to host
Data from device to host (MISO)
Table 17 SPI Interface Signals Description
(1)
(2)
SPI_CS selects the device, indicating that the host wants to communicate to the device.
SPI_IRQ is a dual purpose device to host direction line. When SPI communication is in an idle state (no data transfer),
driving SPI_IRQ low indicates to the host the TiWi-SL module has data to pass to it. Driving SPI_IRQ low following a
SPI_CS deassertion indicates that the TiWi-SL module is ready to receive data.
The information in this document is subject to change without notice.
330-0085-R3.0
Copyright ? 2011-2012 LS Research, LLC
Page 20 of 39
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